Selected U.S. Patent Abstracts

Abstract: Volume of a working liquid in a sensing chamber is measured via a first mechanical resonance frequency. A second resonance may be measured to discriminate interacting volume and density effects, yielding corrected volume, density, and liquid mass. A probability of bubbles present in the liquid is indicated by an abnormal combination of first and second resonances. Determination of a frequency and an associated phase angle near a resonance may be used to discriminate interacting volume and viscosity effects, yielding corrected volume and viscosity. One boundary of the sensing chamber is a deformable plate, which may be rippled to increase the range of linear volumetric compliance. A second boundary paralleling the plate captures a thin variable-thickness fluid layer. Vibrations in the plate cause amplified fluid vibrations parallel to the plate surface, causing a high, thickness-sensitive fluid inertia that lowers plate resonance frequencies in a volume-sensitive manner. A transducer coupled to the resonant plate transforms the mechanical resonances into electrical resonances, which are electronically transformed into frequency readings. A first elastic barrier may contain liquid in a separable disposable container and conform directly to the mated vibrating plate, or to a second elastic barrier, which may be used, first, to retain working liquid on the sensing chamber side, and second, to couple volume changes via the working liquid into the sensing chamber from a second, measured liquid on the disposable side.

Abstract: An enhanced bipolar-transistor apparatus for protecting electronic devices from electrostatic discharge damage. The apparatus is built around a bipolar transistor coupled between a power rail and the circuit to be protected. The protection is based on the high-current-capacity path through the bipolar transistor which is opened up either by collector-to-emitter punch-through in the bipolar transistor or by the bipolar transistor going into normal conduction upon being turned on by a switch coupled to the base of the bipolar transistor. In the preferred embodiment the switch is a MOS transistor that is designed to undergo source-to-drain breakdown at a fixed threshold voltage, whereupon it activates the bipolar transistor which in turn discharges the overvoltage. In this way the advantages of the high-current-capacity bipolar transistor are obtained without the concern that fabrication vagaries will prevent the bipolar transistor from providing needed protection, such as is the situation where the punch-through phenomenon alone is relied on.

Abstract: A digital-to-analog conversion device that has one or more conversion cells, each cell coupled to a master voltage source and to a specific binary input element. The conversion cells include binary-weighted or binary-sized output transistors such that each output transistor, when called upon, delivers a unique analog output current corresponding to a particular binary signal. The master potential provided by a stable source is supplied to the control nodes of the output transistors so that the potential at those control nodes remains constant. Switching on and off of the output transistors is achieved by regulating the sources of those transistors rather than their gates. By regulating the operation of the output transistors at their sources, the present invention provides a digital-to-analog converter and a conversion method with little switching noise and minimal switching delay. The introduction of bipolar transistor devices to regulate the source and control nodes of the MOS output transistors utilizes the best characteristics of both transistor types to enhance converter monotonicity and linearity, in addition to reducing noise.

Abstract: A chimney flue cleaning apparatus that involves use of a rotating chain suspended from the outlet of the chimney and depending to the bottom of the chimney through which means is provided for the attachment of an ordinary drill tool to the chain through use of a flexible cable extension with a detachable connection for the lower end of the chain. At times when the cleaning is to be done the electric drill is connected into its clamp coupling to the end of the cable extension that is journaled in the chimney wall so that high rotation is given to the chain to extend chain element from the rotating chain that will with whipping washing action engage the inner surface of the chimney to remove hardened soot therefrom.

Abstract: An output buffer circuit with edge-rate control capable of maintaining both rising and falling edge-rates within narrow specifications in the face of wide variations in load impedance. In particular, the output buffer of the present invention is intended for coupling to a common bus whereby it may be presented with very low resistive impedance loads and varying capacitive loads. The control schemes for both the pull-up and the pull-down parts of the circuit of the present invention utilize in part fixed currents charging a selected capacitance in order to achieve a metering of the charging or discharging current at the buffer's output. For the pull-down part of the circuit a dual MOS/Bipolar pull-down scheme is used, with the MOS transistors sequentially turning on in a gradual fashion so as to smooth the onset of current sinking. Subsequently, after a measured delay, a bipolar pull-down transistor is turned on. There is also a contingent bipolar pull-down transistor to aid in switching the buffer output from logic-high to logic-low if the MOS transistors and first bipolar transistor acting together are not sufficient. Later, as current-sinking is being turned off, there is again a sequential deactivation of the pull-down transistors so as to round the turn-off curve. The dual MOS/bipolar pull-down scheme provides a degree of temperature compensation of the pulldown current and a lower output capacitance than when one type of transister is used.

Abstract: A grid-frame stabilizer and method of operation for an electrostatic precipitator includes a rigid stand-off member that prevents oscillation of a grid frame used to keep discharge electrodes of the precipitator separated from one another. One end of the stand-off member is rigidly connected to the grid frame and the other end is rigidly connected to a fixed housing component through at least one electrical isolator. The fixed housing component is firmly affixed to an interior region of the precipitator. The stand-off member passes into the housing component through a housing opening which is preferably sealed by a membrane designed to prevent particle contamination of the surfaces of the electrical isolators.

Abstract: A translator circuit for converting from a first logic-level range to a second logic-level range, as is generally involved in the translation from an ECL stage to a CMOS stage. The translator includes a reference stage that provides a reference voltage that is coupled to the CMOS logic stage as well as the ECL logic stage. The ECL logic stage is indirectly coupled between a high potential power rail and a low potential power rail through a plurality of transistors. The CMOS stage is coupled to the ECL stage through two emitter-follower transistors. The CMOS stage uses current-mirroring techniques in combination with the isolated reference stage to effect a translation from the ECL logic level to the CMOS logic level. The CMOS stage also provides relatively fast propagation time which may be set, within certain limits, to a desired time. The reference stage provides an output signal to the gates of the transistors of the CMOS stage through a bipolar transistor that minimizes impedance and isolates the reference stage from switching noise. Use of the bipolar transistor in the reference stage permits fan out to a plurality of output stages through the use of a single reference stage of the present invention.

Abstract: A three-state output buffer circuit with built-in protection against power-rail corruption by bus-imposed voltages when the buffer is in its high-impedance state. In particular the invention protects the high-potential power rail of the high-Z buffer against voltages appearing at the buffer's output node which exceed the voltage of the buffer's high-potential rail. It prevents this overvoltage from finding its way to the power-rail, and thus has application to those situations where a common bus is coupled to a variety of circuits including, for example, 3.3-volt buffers and 5-volt buffers. The invention provides this protection without the "dead zone" of prior-art and related-art circuits. Furthermore, the present invention also has application where it is the low-potential power rail that needs protecting, in situations where the bus may impose voltages at the buffer's output node that are lower than the voltage of the buffer's low-potential power rail. The protection circuit utilizes a pseudo-power rail which can be used to adjust the bias on the output transistor's bulk and so to prevent a leakage path from occurring between the output node and a power rail via the output transistor source/bulk junction. To minimize or avoid a "dead zone" in the charging of the pseudo-rail, a one-way link is established directly between the power rail and the pseudo-power-rail.

Abstract: A MOS-based current-switch/driver multiplexed and coupled with a tapped delay line so as to form a generator for transmitting on unshielded, unfiltered transmission lines highly-symmetric data pulses displaying minimal transient aberrations and minimal common-mode noise. The switch/driver is a basic differential current switch incorporating two MOS output transistors controlled by a novel switching means. The novel switching means ensures the symmetry of the output signals by compensating for the turn-on/turn-off asymmetries inherent in MOS transistors. The compensation is provided by the control circuit interposed between the switch/driver inputs and the control gates of the output transistors, a control circuit which includes deliberately-skewed CMOS inverters and a pair of MOS driver-transistors associated with each output transistor. The output signals from these current generators are referenced to ground. Transient aberrations are largely eliminated in this invention by lengthening the rise and fall times of the transmitted pulses. A tapped delay line is used in conjunction with a plurality of the new switch/drivers in order to form and transmit composite pulses with rise/fall significantly greater than the natural rise-times and fall-times of the individual switches (about 0.6 nsec).

Abstract: A transient-eliminating circuit for minimizing simultaneous conduction through the pullup and pulldown transistors of a buffer circuit. In a buffer circuit used to translate logic signals from circuits supplied by one high-potential power rail to circuits supplied by another high-potential power rail, in which the potentials of the two high-potential rails are not equal, the transient-eliminating circuit is coupled between the output stage and the input stage in such a way that the translator can be utilized independent of power-up sequencing and without any static current I(CCt). The transient-eliminating circuit minimizes simultaneous conduction through the pullup and pulldown transistors of the translator by delaying the turn-on of the pulldown transistor until the pullup transistor is completely off. This is achieved in the preferred embodiment of the invention by coupling an NMOS transistor to the output of the translator circuit to act as an early pulldown on the output by using that NMOS transistor to control a PMOS transistor which is in turn used to control the pulldown transistor. A second NMOS transistor of the transient-eliminating circuit also acts to control the pulldown transistor by operating in the reverse mode of the first NMOS transistor so as to ensure that the NMOS transistor is completely off when required.

Abstract: A circuit for translating logic signals from circuits supplied by one high-potential power rail to circuits supplied by another high-potential power rail in which the potentials of the two high-potential rails are not equal. The translator of the present invention is utilized in the transition from a 3V-supplied circuit to a 5V-supplied circuit, or vice versa, without any static current I(CCt) and regardless of the power-up sequencing. The static current is eliminated by isolating the output of the first stage of the translator, which is at the first high-potential power rail level, from all transistors of the second stage that are tied directly to the second high-potential power rail. In the preferred embodiment of the invention the transistors of the second stage that are powered by the second high-potential power rail are PMOS transistors and the isolation is achieved by linking those PMOS transistors to the first stage through a series of controlling NMOS transistors. In that way, the PMOS transistors will be completely turned off when necessary so as to avoid any undesirable conduction paths occurring due to differences in the potentials of the two high-potential power rails.

Abstract: A broadband low-gain system for automatically frequency-locking a signal where the system uses digital and analog devices and techniques. The system includes a comparator, an up/down counter, a digital-to-analog converter, a decoder, a ring oscillator and a downcounter. The digital control signal is provided by the decoder and actuates one of a plurality of ring oscillator stages. The analog control signal is provided by the digital-to analog-converter and controls a fine-tune mechanism in the actuated stage. The system includes a master reset for clearing the counters.

Abstract: Low-cost apparatus and method for achieving a moderately-precise resistance value into an integrated circuit without the use of resistive trimming or complex feedback loops. The invention has direct application to the production of integrated BiCMOS circuits making use of Delay Lines and/or Voltage-Controlled Ring Oscillators where a +/-10% tolerance in delay time or frequency is acceptable. When incorporated into a PLL, it also presents advantages where tighter tolerances are required, because of its low inherent jitter. By the use of a single off-chip component, this invention overcomes variations in the operating circuit otherwise arising from chip fabrication irregularities, power supply voltage fluctuations, and ambient temperature drift. In the Preferred Embodiment of the present invention, the resistive element is used as the load resistor of a high-frequency ECL delay cell; the element is a controlled MOSFET resistor in parallel with a fixed diffusion resistor. This parallel resistor is made into a compensated calibrated resistor by coupling it into a current mirroring circuit and an external resistor of a precise value. In its Preferred Embodiment, the invention combines the mirroring of current and resistance into a delay cell with the use of an oxide capacitor (a MOSCAP) as the capacitive part of the delay cell's RC time constant and in so doing achieves a delay cell with a delay time which is predictable to within +/-10% without the use of any complex feedback loops, such as occur in a Phase-Locked Loop.

Abstract: A dressing-aid-and-transfer device for assisting attendants and patients in moving and dressing. The device includes a space frame with support legs of the space frame defining a device perimeter. A chest support is provided to support the weight of the patient being moved. The space frame is designed so as to provide a stable and lightweight transferral device that is transportable and easy for a single person to operate. The support legs and reinforcing cross-pieces are configured to provide structurally stability without interfering with an attendant's ability to easily remove and place clothing on a patient's lower body. The support legs pivot at the base of the space frame in order to reduce the force required to transfer a patient to and from a sitting position. Optional features include a rotatable base and the use of actuators to reduce the effort required to tilt the space frame.